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FEATURES 50 Mbps to 2.7 Gbps Operation Typical Rise/Fall Time 80 ps Bias Current Range 2 to 100 mA Modulation Current Range 5 to 80 mA Monitor Photodiode Current 50 A to 1200 A Closed-Loop Control of Power and Extinction Ratio Laser Fail and Laser Degrade Alarms Automatic Laser Shutdown, ALS Dual MPD Functionality for DWDM Optional Clocked Data Full Current Parameter Monitoring 5 V Operation 48-Lead LFCSP Package 32-Lead LFCSP Package (Reduced Functionality) APPLICATIONS DWDM Dual MPD Wavelength Fixing SONET OC-1/3/12/48 SDH STM-1/4/16 Fibre Channel Gigabit Ethernet
Dual-Loop 50 Mbps-2.7 Gbps Laser Diode Driver ADN2841
GENERAL DESCRIPTION
The ADN2841 uses a unique control algorithm to control both the average power and extinction ratio of the laser diode (LD) after initial factory setup. External component count and PCB area are low, since both power and extinction ratio control are fully integrated. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). The ADN2841 has circuitry for a second monitor photodiode, which enables DWDM wavelength control.
FUNCTIONAL BLOCK DIAGRAM
IMPDMON2 DEGRADE IMPDMON
VCC
IMMON
IBMON
CLKSEL
GND
FAIL
ALS
VCC
IMODN
VCC LD IMODP
VCC MPD IMPD IMOD IMPD2 CONTROL GND PSET IBIAS GND ERSET
DATAP DATAN CLKP CLKN IBIAS ASET
ADN2841
GND ERCAP PAVCAP IDTONE LBWSET
GND
GND
GND
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADN2841-SPECIFICATIONS
Parameter
(VCC = 5 V 10%. All specifications TMIN to TMAX, unless otherwise noted1. Typical values as specified at 25 C.)
Min Typ Max Unit Conditions/Comments
LASER BIAS (BIAS) Output Current IBIAS Compliance Voltage IBIAS during ALS ALS Response Time CCBIAS Compliance Voltage MODULATION CURRENT (IMODP, IMODN) Output Current IMOD Compliance Voltage IMOD during ALS Rise Time Fall Time Jitter Pulsewidth Distortion MONITOR PD (MPD, MPD2) Current Input Voltage POWER SET INPUT (PSET) Capacitance Input Current Voltage EXTINCTION RATIO SET INPUT (ERSET) Allowable Resistance Range Voltage ALARM SET (ASET) Allowable Resistance Range Voltage Hysteresis CONTROL LOOP Time Constant DATA INPUTS (DATAP, DATAN, CLKP, CLKN) AC-Coupled2 V p-p (Single-Ended Peak-to-Peak) Input Impedance tSETUP3 tHOLD3 LOGIC INPUTS (ALS, LBWSET, CLKSEL) VIH VIL ALARM OUTPUTS (Internal 30 k Pull-Up) VOH VOL IDTONE Compliance Voltage
IOUT I IN RATIO
2 1.2 10 1.2 5 1.8 80 80 18 50
100
VCC
0.1
mA V mA s V mA V mA ps ps ps p-p ps A V pF A V k V k V % sec sec (LBWSET = GND) (LBWSET = VCC) Average Current
80 VCC 0.1 120 120 20
1200 1.6 80 1200 1.35 25 1.35 25 1.35
50 1.15 1.2 1.15 1.2 1.15
Average Current
1.23
1.23
1.23 5 0.22 2.25
100 150 0 2.4 50 95 -70
500
mV ps ps V V V V V User to Supply Current Sink in the Range 50 A to 4 mA
0.8 2.4 0.8 VCC - 1.5 2 0.01 1
fIN4
MHz
-2-
REV. A
ADN2841
Parameter Min Typ Max Unit Conditions/Comments
IBMON, IMMON, IMPDMON, IMPDMON2 IBMON, IMMON Division Ratio IMPDMON, IMPDMON2 IMPDMON to IMPDMON2 Matching Compliance Voltage SUPPLY ICC5 VCC6
100 1 0 0.05 5.0 1 VCC - 1.2
A/A A/A % V A V
IMPD = 1200 A
IBIAS = IMOD = 0
4.5
5.5
NOTES 1 Temperature range: -40C to +85C. 2 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin. 3 Guaranteed by design and characterization. Not production tested. 4 IDTONE may cause eye distortion. 5 ICC for power calculation is the typical I CC given. 6 All VCCS should be shorted together. Specifications subject to change without notice.
SETUP HOLD
tS
DATAP/DATAN
tH
CLKP
Figure 1. Setup and Hold Time
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . -65C to +150C Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . 150C 48-Lead LFCSP Package Power Dissipation . . . . . . . . . . . . . . .(TJ MAX - TA)/JA mW JA Thermal Impedance2 . . . . . . . . . . . . . . . . . . . . 25C/W Lead Temperature (Soldering for 10 sec) . . . . . . . . 300C
32-Lead LFCSP Package Power Dissipation . . . . . . . . . . . . . . . (TJ MAX - TA)/JA mW JA Thermal Impedance2 . . . . . . . . . . . . . . . . . . . . 32C/W Lead Temperature (Soldering for 10 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents of up to 100 mA will not cause SCR latch-up. 2 JA is defined when the part is soldered onto a four-layer board.
ORDERING GUIDE
Model ADN2841ACP-32 ADN2841ACP-48 ADN2841ACP-32-RL ADN2841ACP-32-RL7 ADN2841ACP-48-RL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 32-Lead LFCSP 48-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 48-Lead LFCSP
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2841 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADN2841
PIN CONFIGURATIONS 48-Lead LFCSP
36 GND2 35 IDTONE 34 GND2 33 IBMON 32 IMMON 31 GND3 30 VCC3 29 ALS 28 FAIL 27 DEGRADE 26 CLKSEL 25 GND
32-Lead LFCSP
32 CCBIAS 31 IBIAS 30 GND2 29 GND2 28 IMODP 27 GND2 26 IMODN 25 VCC2
PIN 1 INDICATOR
GND 1 LBWSET 2 ASET 3 ERSET 4 PSET 5 GND 6 IMPD 7 IMPDMON 8 IMPDMON2 9 IMPD2 10 GND4 11 VCC4 12
PIN FUNCTION DESCRIPTIONS
Pin No. 48-Lead 32-Lead 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6
Mnemonic GND LBWSET ASET ERSET PSET GND IMPD IMPDMON IMPDMON2 IMPD2 GND4 VCC4 ERCAP PAVCAP GND VCC1 GND1 DATAN DATAP GND1 CLKP CLKN GND GND GND CLKSEL DEGRADE FAIL ALS VCC3 GND3 IMMON IBMON GND2 IDTONE GND2
Function Supply Ground Select Low Loop Bandwidth (Active = VCC) Alarm Current Threshold Setting Pin Extinction Ratio Set Pin Average Optical Power Set Pin Ground Monitor Photodiode Input Mirrored Current from Monitor Photodiode Mirrored Current from Monitor Photodiode 2 (for Use with Two MPDs) Monitor Photodiode Input 2-(for Use with Two MPDs) Supply Ground Supply Voltage Extinction Ratio Loop Capacitor Average Power Loop Capacitor Ground Supply Voltage Supply Ground Data, Negative Differential Terminal Data, Positive Differential Terminal Supply Ground Data Clock Positive Differential Terminal, used if CLKSEL = VCC Data Clock Negative Differential Terminal, used if CLKSEL = VCC Ground Ground Ground Clock Select (Active = VCC), used if data is clocked into chip DEGRADE Alarm Output FAIL Alarm Output Automatic Laser Shutdown Supply Voltage Supply Ground Modulation Current Mirror Output Bias Current Mirror Output Supply Ground IDTONE (Requires External Current Sink to Ground) Supply Ground -4- REV. A
7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
ERCAP 9 PAVCAP 10 VCC1 11 DATAN 12 DATAP 13 GND1 14 CLKP 15 CLKN 16
GND2 37 VCC2 38 IMODN 39 IMODN 40 GND2 41 IMODP 42 IMODP 43 GND2 44 GND2 45 IBIAS 46 IBIAS 47 CCBIAS 48
ADN2841
TOP VIEW (Not to Scale)
24 GND 23 GND 22 CLKN 21 CLKP 20 GND1 19 DATAP 18 DATAN 17 GND1 16 VCC1 15 GND 14 PAVCAP 13 ERCAP
LBWSET 1 ASET 2 ERSET 3 PSET 4 IMPD 5 IMPDMON 6 GND4 7 VCC4 8
PIN 1 INDICATOR
ADN2841
TOP VIEW (Not to Scale)
24 IBMON 23 IMMON 22 GND3 21 VCC3 20 ALS 19 FAIL 18 DEGRADE 17 CLKSEL
ADN2841
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. 48-Lead 32-Lead 37 38 39 40 41 42 43 44 45 46 47 48 25 26 27 28 29 30 31 32
Mnemonic GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS IBIAS CCBIAS
Function Supply Ground Supply Voltage Modulation Current Negative Output. Connect to 25 . Modulation Current Negative Output. Connect to 25 . Supply Ground Modulation Current Positive Output. Connect to laser diode. Modulation Current Positive Output. Connect to laser diode. Supply Ground Supply Ground Laser Diode Bias Current Laser Diode Bias Current Extra Laser Diode Bias when AC-Coupled
REV. A
-5-
ADN2841
GENERAL LOOP BANDWIDTH SELECTION
Laser diodes have current-in to light-out transfer functions as shown in Figure 2. Two key characteristics of this transfer function are the threshold current, ITH, and the slope in the linear region beyond the threshold current, referred to as slope efficiency, LI.
ER = P1 P0 P1 PAV = P1 + P0 2
OPTICAL POWER
P PAV I P0 ITH CURRENT LI = P I
For anyrate operation, the user should hardwire the LBWSET pin high and use 1 F capacitors to set the actual loop bandwidth. These capacitors are placed between the PAVCAP and ERCAP pins and ground. It is important that these capacitors be low leakage multilayer ceramics with an insulation resistance greater than 100 G or a time constant of 1000 sec, whichever is less. The ADN2841 may be optimized for 2.7 Gbps operation by keeping the LBWSET pin low. This results in a much shorter loop time constant (a 10 reduction). The value of PAVCAP and ERCAP capacitors required for 2.5 Gbps operation is 22 nF.
ALARMS
Figure 2. Laser Transfer Function
CONTROL
A monitor photodiode (MPD) is required to control the LD. The MPD current is fed into the ADN2841 to control the optical power and extinction ratio, continuously adjusting the bias current and modulation current in response to the laser's changing threshold current and light-to-current (LI) slope (slope efficiency). The ADN2841 uses automatic power control (APC) to maintain a constant power over time and temperature. The ADN2841 uses closed-loop extinction ratio control to allow optimum setting of extinction ratio for every device. Therefore, SONET/SDH interface standards can be met over device variation, temperature, and time. Closed-loop modulation control eliminates the need to either overmodulate the LD or include external components for temperature compensation. This reduces research and development time and second-sourcing issues caused by characterizing LDs. Average power and extinction ratio are set using the PSET and ERSET pins, respectively. Potentiometers are connected between these pins and ground. The potentiometer R PSET is used to change the average power. The potentiometer RERSET is used to adjust the extinction ratio. Both PSET and ERSET are kept 1.23 V above GND. RPSET and RERSET can be calculated using the following formulas:
The ADN2841 alarms are designed to allow interface compliance to ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). The ADN2841 has two active high alarms, DEGRADE and FAIL. A resistor between ground and the ASET pin is used to set the current at which these alarms are raised. The current through the ASET resistor is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will be raised at 90% of this level. Example:
IFAIL = 50 mA IDEGRADE = 45 mA
I ASET = RASET = I BIASTRIP 50 mA = = 500 A 100 100 1.23V 1.23V = = 2.46 k I ASET 500 A
NOTE: The smallest value for RASET is 1.2 k, as this corresponds to the IBIAS maximum of 100 mA. The laser degrade alarm, DEGRADE, gives a warning of imminent laser failure if the laser diode degrades further or environmental conditions, e.g., increasing temperature, continue to stress the LD. The laser fail alarm, FAIL, is activated when the transmitter can no longer be guaranteed to be SONET/SDH compliant. This occurs when one of the following conditions arises: * The ASET threshold is reached. * The ALS pin is set high. This shuts off the modulation and bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system in which ALS has been enabled. DEGRADE will only be raised when the bias current exceeds 90% of ASET current.
MONITOR CURRENTS
1.23 V I AV where IAV is the average MPD current. RPSET =
1.23V I MPD -CW ER - 1 x x 0.2 x PAV PCW ER + 1 where PCW is the dc optical power specified on the laser data sheet, IMPD_CW is the MPD current at that specified PCW, and PAV is the required average power. RERSET = Note that IERSET and IPSET will change from device to device. However, the control loops will determine actual values. It is not required to know the exact values for LI or MPD optical coupling.
IBMON, IMMON, IMPDMON, and IMPDMON2 are current controlled current sources from VCC. They mirror the bias, modulation, and MPD current for increased monitoring functionality. An external resistor to GND gives a voltage proportional to the current monitored.
DUAL MPD DWDM FUNCTION (48-LEAD LFCSP ONLY)
The ADN2841 has circuitry for an optional second monitor photodiode, MPD2.
-6-
REV. A
ADN2841
REF CLOCK 20MHz- 180MHz
CLKIN IOUT
10kHz-1MHz 1.25mA-20mA LP FILTER (DC-COUPLED) 50 1/2 IOUT 50 500 BC550 IDTONE
AD8602
0.125mA-2mA
AD9850/AD9851
DDS
RSET
ADN2841
37.5 A-600 A
AD8602
BC550 1/2
50 A-800 A IMMON 1000
CONTROLLER
1300
Figure 3. Circuitry to Allow Fiber Identification
The second photodiode current is mirrored to IMPDMON2 for wavelength control purposes and is summed internally for the power control loop. For single MPD circuits, the MPD2 pin is tied to GND. This enables the system designer to use the two currents to control the wavelength of the laser diode using various optical filtering techniques inside the laser module. If the monitor current functions, IMPDMON and IMPDMON2 are not required, the IMPD and IMPD2 pins can be grounded, and the monitor photodiode output can be connected directly to PSET.
IDTONE (48-LEAD LFCSP ONLY)
ADN2841
DATAP TO FLIP-FLOPS DATAN 50 50 VREG R R = 2.5k , DATA R = 3k , CLK
400 A TYP
The IDTONE pin is supplied for fiber identification/supervisory channels or control purposes in WDM. This pin modulates the optical one level over a possible range of 2% of minimum IMOD to 10% of maximum IMOD. The level of modulation is set by connecting an external current sink between the IDTONE pin and ground. There is a gain of two from this pin to the IMOD current. Figure 3 shows how an AD9850/AD9851 DDS may be used with the ADN2841 to allow fiber identification. Note that using IDTONE during transmission may cause optical eye degradation.
DATA, CLOCK INPUTS
Figure 4. AC-Coupling of Data Inputs
CCBIAS
CCBIAS should be connected to the BIAS pin if the laser diode is connected to the ADN2841 using a capacitor. CCBIAS is a current sink to GND.
AUTOMATIC LASER SHUTDOWN
The ADN2841 ALS allows compliance to ITU-T-G958 (11/94), section 9.7. When ALS is logic high, both bias and modulation currents are turned off. Correct operation of ALS can be confirmed by the fail alarm being raised when ALS is asserted. Note this is the only time that DEGRADE will be low while FAIL is high.
Data and clock inputs are ac-coupled (10 nF recommended) and terminated via a 100 internal resistor between DATAP and DATAN and also between CLKP and CLKN pins. There is a high impedance circuit to set the common-mode voltage that is designed to change overtemperature. It is recommended that ac-coupling be used to eliminate the need for matching between common-mode voltages.
REV. A
-7-
ADN2841
ALARM INTERFACES
VCC
A 30 k internal pull-up resistor is employed to pull the digital high value of the alarm outputs to VCC. However, the ADN2841 has a feature that allows the user to externally wire resistors in parallel with the 30 k pull-up resistors, thus enabling the user to interface to non-VCC levels. Non-VCC alarm output levels must be below the VCC used for the ADN2841.
POWER CONSUMPTION
VCC
IMPD
VCC
ADN2841
ADN2850
TX RX CLK CS SDI SDO CLK CS DAC1 DAC2 PSET ERSET IMODP IBIAS
The ADN2841 die temperature must be kept below 125C. The JA is 25C/W for the 48-lead LFCSP and 32C/W for the 32-lead LPCSP when soldered in a four-layered board. Both LFCSP packages have an exposed paddle and as such need to be soldered to the PCB to achieve this thermal performance.
T DIE = T AMBIENT + JA x P I CC = I CCMIN + 0.3 I MOD
DATAP DATAN IDTONE
P = VCC x I CC + I BIAS x V BIAS
(
_ PIN
) + (I
MOD
x V MOD _ PIN
)
Thus the maximum combination of IBIAS + IMOD must be calculated.
Figure 5. Application Using Optical Supervisor ADN2850 as a Dual 10-Bit Digital Potentiometer Using Thin-Film Resistor Technology to Give Very Low Temperature Coefficients
IDTONE
FAIL DEGRADE CLKN CLKP DATAP DATAN 100nF
VCC
VCC
GND2
VCC 25 37
36
GND2 IBMON IMMON IDTONE GND3 VCC3
GND
25 24
GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS IBIAS
ALS FAIL DEGRADE CLKSEL
GND GND CLKN CLKP GND1
GND
FU-445SDF-WM1 VCC
ADN2841
DATAP DATAN GND1 VCC1 GND PAVCAP ERCAP
VCC
CCBIAS 48 VCC 1
IMPD IMPDMON IMPDMON2 IMPD2
LBWSET ASET ERSET PSET
GND
GND
12
GND4
1.5k
VCC4
13
VCC
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED.
100nF GND
100nF
100nF
DATAN
DATAP
10 F
Figure 6. 2.7 Gbps Test Circuit, DC-Coupled, Data Not Clocked, Fast Loop Time Constant Selected
-8-
REV. A
ADN2841
VCC FAIL DEGRADE
VCC
GND2
VCC 25 VCC VCC 37
GND IDTONE GND2 IBMON IMMON GND3 VCC3 ALS FAIL DEGRADE CLKSEL
36
25
GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS CCBIAS 48 1
GND GND CLKN CLKP GND1
24
GND CLKN CLKP DATAP DATAN
VCC VCC
ADN2841
DATAP DATAN GND1 VCC1 GND PAVCAP ERCAP
GND LBWSET ASET ERSET PSET
IBIAS
IMPD IMPDMON IMPDMON2 IMPD2
GND
12
VCC4
VCC
1.5k
GND4
13
VCC
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED.
100nF GND
100nF
100nF
100nF
10 F
Figure 7. Anyrate Test Circuit, Capacitively Coupled, Data Clocked, Slow Loop Time Constant Selected
REV. A
-9-
ADN2841
VCC VCC VCC EA MODULATOR 75 33 NOTES 1. V CCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2841 AND THE LASER DIODE USED. 2. THE OP293 HAS BEEN SELECTED BECAUSE OF ITS GAIN-BANDWIDTH PRODUCT AND SHOULD BE USED IN THIS APPLICATION.
10nF VCC 100nH
CCBIAS
VCC
IMODN
IMODN
IMODP
IMODP
GND2
GND2
GND2
GND2
IBIAS
IBIAS
VCC2
48 1
36 GND2 VCC
GND ASET VCC ERSET PSET GND IMPD
LBWSET
IDTONE GND2 IBMON IMMON GND3 VCC3 ALS FAIL DEGRADE CLKSEL
ADN2841
VCC
IMPDMON IMPDMON2 IMPD2
ERCAP
DATAN
DATAP
GND1
GND1
CLKN
GND4
PAVCAP
CLKP
GND
VCC1
12 VCC VCC 8 1 3 1/2 OP293 1/2 OP293 7 6 5 2 VCC
GND
VCC4
GND 24 VCC
DAC
1k
DAC
1k
-VCC
Figure 8. Applications Circuit
Figure 9. Unfiltered 2.5 Gbps Optical Eye. Average Power = -3 dBm, Extinction Ratio = 9.5 dB. Eye Obtained Using a Mitsubishi FU-445-SDF.
Figure 10. Filtered 2.5 Gbps Optical Eye. Average Power = -3 dBm, Extinction Ratio = 9 dB. Eye Obtained Using a Mitsubishi FU-445-SDF.
-10-
REV. A
ADN2841
OUTLINE DIMENSIONS 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)
Dimensions shown in millimeters
0.30 0.23 0.18
48 1
7.00 BSC SQ
0.60 MAX 0.60 MAX
37 36
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTOM VIEW
5.25 4.70 2.25
0.50 0.40 0.30 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08
25 24
12 13
1.00 0.90 0.80 0.25 REF
5.50 REF
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
32-Lead Frame Chip Scale Package [LFCSP] (CP-32)
Dimensions shown in millimeters
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 12 MAX 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 REF COPLANARITY 0.08
17 16
9
3.50 REF
1.00 0.90 0.80 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
REV. A
-11-
Revision History
Location 8/02--Data Sheet changed from REV. 0 to REV. A. Page
Figure 8 replaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C02659-0-9/02(A) PRINTED IN U.S.A.
Updated Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
-12-
REV. A

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